DRD-GFs

Introduction

  • 24bit DSP core : fixed-point, max 100MHz operation
  • Memory :
    • 1KW data RAM
    • 1.5KW program RAM ( program / data )
    • 2.5KW OPT ROM ( program / data ) : 1.8 and 6.5 Volt power for program, 40MHz operation
    • 2.5KW program ROM
  • Peripherals
    • I2S interface
    • I2C interface
    • 3 Times : count by DSP clock / I2S bit clock / I2S left-right clock
    • GPIO : 6-bit
  • Power-down modes
  • PLL : 1 PLL for DSP core clock generation
  • Package : SOIC 28-pin

DRD-GFs chip block diagram
DRD-GFs Block Diagram

 

DRD-GFs 28-pin package
DRD-GFs 28-pin package